library ieee;
use ieee.std_logic_1164.all;

entity display is
	port(
        instr : in std_logic_vector(15 downto 0);
        ac : in std_logic_vector(7 downto 0);
        pc : in std_logic_vector(7 downto 0);
        -- 以hex的形式分别显示AC PC 和 当前指令
		display_out: out std_logic_vector(55 downto 0)
	);
end display;

architecture Behavioral of display is
component seven_seg is
    port(
        binary : in std_logic_vector(3 downto 0);
        seg : out std_logic_vector(6 downto 0)
    );
end component;
begin
    ac_1 : seven_seg port map(ac(7 downto 4), display_out(55 downto 49));
    ac_2 : seven_seg port map(ac(3 downto 0), display_out(48 downto 42));
    pc_1 : seven_seg port map(pc(7 downto 4), display_out(41 downto 35));
    pc_2 : seven_seg port map(pc(3 downto 0), display_out(34 downto 28));
    instr_1 : seven_seg port map(instr(15 downto 12), display_out(27 downto 21));
    instr_2 : seven_seg port map(instr(11 downto 8), display_out(20 downto 14));
    instr_3 : seven_seg port map(instr(7 downto 4), display_out(13 downto 7));
    instr_4 : seven_seg port map(instr(3 downto 0), display_out(6 downto 0));
end Behavioral;

